1. Field of Invention
The invention relates generally to analog-to-digital conversion of a signal, and more specifically to apparatuses and methods pertaining to an analog-to-digital converter (ADC) which can span a wide range of input frequency range, i.e., large bandwidth.
2. Art Background
In the field of electronics, signals exist in an analog form or in a digital form. The analog signal is said to have a continuous variation with respect to an independent variable such as time or space, etc. An amplitude of an analog signal typically represents some information of interest. Variation in time is characterized in some cases by sinusoidal variation. The digital signal is characterized in the simplest form as a signal which exists in two states. Zero (0) and one (1) are two states commonly associated with a digital signal. Digital signals can also be configured to take on more than two states and in such cases digital signals are constructed to have a number of states that are a power of 2. A code using the number of desired states in the digital signal is used to encode the digital signal with the information of interest.
Electronic devices such as computers, mobile phones, tablets, network equipment, communication channels, etc. often utilize an analog-to-digital converter (ADC) which converts a signal from the analog form to the digital form. As electronic devices become faster, clock frequencies associated with the systems increase. Increasing clock frequency require an internal clock to operate at higher and higher frequencies, this requirement increases the bandwidth required for an ADC used in the system. Higher ADC bandwidths usually result in increased power consumption. This can present a problem.
Some existing analog-to-digital converters (ADCs) are made to satisfy the Nyquist sampling theorem, thereby providing a sampling clock with a frequency at least twice as large as the highest analog frequency input thereto, sometimes referred to as the Nyquist frequency. Some examples of ADCs which are designed to accomplish Nyquist sampling are known in the art as Flash ADC, Pipelined ADC, SAR (Successive Approximation Register) ADC, Single-slope ADC, Dual-Slope ADC, and Sigma-Delta ADCs. ADCs that use a capacitive array place the capacitive array on the input pin such as an input pin into a comparator, sense amplifier, etc. An example of a SAR ADC is shown in FIG. 1 note that input 102 and 104 are directly in-line with capacitive array 106. FIG. 2 illustrates an example of a Pipelined ADC where capacitor 202 C2 is directly in-line with input 204. Existing capacitive arrays are binary weighted and as such place significant capacitance on the input pin thereby presenting a limitation to the achievable bandwidth of the input analog signals. This can present a problem.
Other ADCs are designed to operate in an under-sampling mode where the clock frequency is less than the Nyquist frequency. In under-sampling mode designs, the high end of the input frequency range of the analog signal can be quite large. For such high-frequency input signals the capacitive loading of the capacitive array becomes the limiting feature for the input signal frequency bandwidth. This can present a problem.
In both Nyquist sampling ADC designs and under-sampling ADC designs when the capacitive array is connected to the input pin of an ADC the bandwidth is reduced, especially with high precision ADCs, i.e., ADCs with a large number of bits, e.g., 8, 12, 24 bit, etc. There are tradeoffs between resolution, speed, silicon size, and power consumption (high precision ADCs need many bits, and the unit capacitor should be large enough to ensure low noise and acceptably small mismatch). Meeting these criteria result in very large capacitive loading on the input pins. Large capacitive loading results in lower bandwidth, longer processing time, and larger power consumption. All of which can present a problem.